1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors used for non-volatile information storage.
2. Description of the Related Art
Integrated circuits typically comprise a great number of circuit elements on a given chip area according to a specified circuit layout, wherein advanced devices may comprise millions of signal nodes that may be formed by using field effect transistors, which may also be referred to herein as MOS transistors. Thus, field effect transistors may represent a dominant component of modern semiconductor products, wherein advances towards increased performance and low integration volume are mainly associated with a reduction of size of the basic transistor structures. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of field effect transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions represented by an interface formed of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices, an increasing amount of storage capacity may be provided on chip within the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. Similarly, in many types of control circuits, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density on the one side versus operating speed on the other side. For instance, fast or temporary buffer memories, so-called cache memories, may be provided in the vicinity of the CPU core, wherein respective cache memories may be designed so as to allow reduced access times compared to external storage devices.
On the other hand, increasingly, non-volatile memories may have to be incorporated in sophisticated semiconductor devices, wherein the flash memory technique represents one promising technology, in which MOS technology may be efficiently applied to forming storage cells. To this end, basically, a field effect transistor is provided, in which transistor operation is controlled, on the other hand, by a gate electrode, as discussed above, which additionally includes a floating gate that is electrically insulated from the control gate electrode and from the channel region and drain region of the field effect transistor. The floating gate represents a dielectric charge storage region within the control gate electrode of the field effect transistor and may hold stationary charge carriers, which in turn influence the current flow behavior of the field effect transistor. The stationary charge carriers in the floating gate may be injected upon establishing a specific operation mode, which is also referred to as programming of the memory cell, in which per se negative effects, such as hot carrier injection and the like, that is, any type of leakage current generating mechanism, may result in the incorporation of charge carriers in the charge storage region. Consequently, in the normal operation mode, the injected charge carriers in the charge storage region may thus significantly affect the current flow through the channel region of the transistor, which may be detected by appropriate control circuitry. On the other hand, upon erasing the memory cell, the charge carriers in the charge storage region may be removed, for instance by establishing appropriate voltage conditions, thereby establishing a detectable different operational behavior of the field effect transistor during the normal operation mode, i.e., during the operation with the standard supply voltages. Although the concept of flash memory cells, i.e., of field effect transistors comprising a floating gate, provides a non-volatile storage mechanism with moderately high information density and low access times, in turns out that further device scaling and compatibility to other sophisticated mask technologies may be difficult to be achieved on the basis of conventional concepts for forming non-volatile storage transistors, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, which may represent any semiconductor device including a flash memory area. For example, the semiconductor device 100 represents a memory chip, a control circuit including a non-volatile memory and the like. For convenience, a single memory cell 150 is illustrated in FIG. 1a, which is provided in the form of a field effect transistor, which may also be referred to herein as a non-volatile storage transistor. The device 100 comprises a substrate 101 and a semiconductor layer 102 formed thereabove, such as a silicon layer and the like. It should be appreciated that the substrate 101 and the semiconductor layer 102 may represent a silicon-on-insulator (SOI) configuration, if a buried insulating layer (not shown) is provided between the substrate 101 and the semiconductor layer 102. In other cases, the semiconductor layer 102 represents a portion of a crystalline material of the substrate 101, thereby providing a bulk configuration. The semiconductor layer 102 comprises a semiconductor region or active region 102A, in and above which the transistor 150 is formed. The active region 102A may be laterally delineated by any appropriate isolation structure (not shown), such as a shallow trench isolation and the like.
The transistor 150 comprises a gate electrode structure 160 formed on the semiconductor region 102A so as to control the current flow between a source region 151 and a drain region 152, by controlling the conductivity state of a channel region 153, which is laterally positioned between the source region 151 and the drain region 152. The gate electrode structure 160 comprises a gate dielectric material 161, which is typically comprised of silicon dioxide or silicon oxynitride, with an appropriate thickness of, for instance, several nanometers in sophisticated applications. Furthermore, a gate electrode 163 is formed on the gate dielectric material 161 and is typically comprised of polysilicon material 163A, possibly in combination with a contact material 163B in the form of a metal silicide, such as nickel silicide. Furthermore, the gate electrode structure 160 comprises a charge storage region 162, typically comprised of silicon nitride, which may also be referred to as a floating gate, since the charge storage region 162 may be embedded in a dielectric material so as to be electrically insulated from the gate electrode 163 and from the channel region 153 and the drain region 152 and may influence the current flow in the channel region 153. For example, the gate dielectric material 161 in combination with an additional dielectric material 161A may provide dielectric encapsulation of the charge storage region 162. Moreover, as illustrated in FIG. 1a, the charge storage region 162 is positioned so as to overlap with a portion of the drain region 152 and a portion of the channel region 153. That is, the charge storage region 162 is positioned at an area in which high energetic charge carriers may be present upon applying appropriate voltages to the drain and source regions 152, 151 and the gate electrode structure 160, which may thus enable the injection or removal of charge carriers to and from the charge storage region 162, as will be described later on in more detail.
Furthermore, the transistor 150 may comprise a sidewall spacer structure 156 formed on sidewalls of the gate electrode 163, which may have any appropriate configuration so as to appropriately define the lateral and vertical profile of the drain and source regions 152, 151. Moreover, as illustrated, contact areas 154, such as metal silicide regions, are provided in the source and drain regions 151, 152.
In the manufacturing stage shown, the semiconductor device 100 further comprises a contact structure 120, which may comprise any appropriate dielectric material or materials, such as a layer 121, for instance in the form of a silicon nitride material, followed by a second dielectric material 122, such as a silicon dioxide material. Additionally, the contact structure 120 comprises contact elements 123 so as to connect to the source and drain regions 151, 152 and to the gate electrode structure 160. It should be appreciated that the contact elements 123 connecting to the source and drain regions 151, 152 and the contact element 123 connecting to the gate electrode structure 160 are typically formed at different levels in a direction perpendicular to the drawing plane of FIG. 1a, i.e., in the direction of the transistor width of the transistor 150.
The semiconductor device 100 is typically formed on the basis of any appropriate process strategy, during which other field effect transistors may also be provided in the device 100. For example, the active region 102A may be formed by providing corresponding isolation structures and establishing a desired basic dopant profile in the region 102A by applying well-established implantation processes and masking techniques. Next, the gate dielectric material 161 may be formed with an appropriate thickness on the transistor 150, while, in other device areas, a reduced thickness may be applied, depending on the overall device requirements. Next, a material for the charge storage region 162 may be provided and may be subsequently patterned on the basis of an appropriate lithography process. Next, dielectric material 161A is formed and may be patterned, depending on the overall process strategy. Thereafter, the electrode material 163A, possibly in combination with further materials, such as hard mask materials, dielectric cap materials and the like, are deposited and may be subsequently patterned on the basis of sophisticated lithography and anisotropic etch techniques. Next, the drain and source regions 151, 152 may be formed, for instance, by a first implantation sequence so as to provide the desired overlap of the regions 151, 152 with the gate electrode structure 160, followed by the deposition and patterning of any appropriate dielectric material for forming the sidewall spacer structure 156, which may then be used as an implantation mask for performing a subsequent implantation process for forming deeper areas of the drain and source regions 151, 152. Based on one or more anneal processes, the final dopant profile is then established and the metal silicide regions 154 and 163B are formed by well-established process techniques. Next, the contact structure 120 may be formed by depositing the materials 121 and 122 and patterning the same so as to form corresponding contact openings, which may be subsequently filled with any appropriate conductive material, such as tungsten and the like, thereby providing the contact elements 123.
FIG. 1b schematically illustrates the semiconductor device 100 in an operating mode, in which the transistor 150 may be programmed. It should be appreciated that the transistor 150 represents an N-channel transistor in the example illustrated, i.e., the source and drain regions 151, 152 are heavily N-doped, while the channel region 153 is P-doped. When programming the transistor 150, i.e., when transferring charge carriers 155A, that is, electrons, into the charge storage region 162, a relatively high programming voltage is applied to the gate electrode structure 160 and the drain 152. For example, 12 volts may be applied and may represent a typical programming voltage. On the other hand, the source region 151 is connected to the low supply voltage of the device 100, i.e., 0 volts. In this operational mode, a conductive channel 155 may build up from the source region 151 via the channel region 153 so as to connect to the drain region 152. That is, electrons start flowing from the source region 151 to the drain region 152 and may thus be subjected to hot carrier injection or any other leakage current mechanisms, in which electrons are gathering sufficient energy so as to move through the dielectric material 161 and to be trapped in the region 162.
FIG. 1c schematically illustrates the device 100 during the normal operating mode, i.e., in an operating mode in which the transistor 150 may be read out in order to determine the state of the transistor 150 and thus the information contained therein, which is associated with the state of the transistor 150. Thus, during this operating mode, the regular supply voltage may be applied, such as 1 volt at the gate electrode structure 160, while the source 151 is at the low supply voltage, i.e., 0 volts. In this case, the positive charges 165 may result in the establishment of a conductive channel 155, which, however, may be pinched off at the drain side 152 due to the presence of the stationary charges 155A, which have previously been programmed into the charge storage region 162. Consequently, a current flow is not established between the source and drain regions 151, 152, and this high impedance state of the transistor 150 may be detected by any appropriate control circuitry (not shown). Hence, since the charges 155A may subsequently not be affected by the typical operating voltages, except for extremely small leakage currents and the like, the charges 155A may be considered as stationary and may thus provide the non-volatile behavior of the transistor 150, that is, even after switching off the supply voltage, the charges 155A may remain trapped within the region 162.
FIG. 1d schematically illustrates the device 100 during an erase cycle, so as to re-write the transistor 150 with an inverse information bit. To this end, a moderately high voltage that is significantly above the typical supply voltage, such as 12 volts, is supplied to drain region 152, while the gate electrode structure 160 is connected to the low supply voltage, i.e., 0 volt. In this case, the charges 155A may be removed from the region 162, for instance by quantum mechanical effects, which are typically known as Fowler-Nordheim tunneling. Hence, the charges 155A may be removed via the channel region 153 and the drain region 152.
FIG. 1e schematically illustrates the device 100 after erasing the transistor 150 during the normal operating mode. Next, upon applying the normal operating voltage to the gate electrode structure 160, for instance 1 volt, the conductive channel 155 may build up and may now extend to the drain region 152, thereby providing a low impedance state for the transistor 150, which may thus be detected by the corresponding control circuitry.
The basic configuration of the transistor 150 may thus provide a non-volatile storage behavior, wherein a single field effect transistor may be sufficient to store at least 1 bit of information, thereby contributing to a high bit density. It turns out, however, that a further scaling of the overall device dimension may result in significant difficulties for the conventional concept, since, for instance, the charge storage region 162 is patterned on the basis of a lithography process, thereby requiring certain minimum dimensions that are within the capability of the sophisticated lithography techniques. Consequently, the length of the gate electrode structure 160 may not be reduced, as is desirable in view of enhancing the overall information density. Moreover, in sophisticated applications, increasingly, superior gate electrode structures are used for standard field effect transistors in order to reduce overall dimensions and increase performance. In these strategies, a high-k dielectric material, i.e., a material having a dielectric constant of 10.0 or higher, is provided in the gate insulation layer, in combination with a metal-containing electrode material, wherein various sophisticated process strategies have been developed, which may not be compatible with the conventional concept of providing a non-volatile storage transistor, such as the transistor 150. For example, so-called replacement gate approaches have been developed, in which the high-k dielectric material in combination with appropriate electrode metals are provided in a very late manufacturing stage, i.e., after completing the basic transistor configuration, which may not be compatible with a conventional storage transistor configuration. Consequently, the efficiency and information density provided by conventional non-volatile storage transistors may not be enhanced in a desired manner, even if highly sophisticated manufacturing strategies are applied for field effect transistors in other device areas.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.